A. Field of the Invention
The present invention relates to an insulated gate bipolar transistor, and more particularly to an insulated gate bipolar transistor having a trench structure in which a gate electrode is buried in a trench formed in a semiconductor substrate with a gate insulator film interposed between.
B. Description of the Related Art
In recent years, under the leadership of Europe and North America, restrictions have been placed on electromagnetic noise generated from semiconductor apparatus provided with power semiconductor devices. It is known that the electromagnetic noise is generated due to variation in a voltage V with respect to time t (hereinafter represented as dV/dt) or variation in a current I with respect to time t (hereinafter represented as dI/dt) when the power semiconductor device is subjected to switching. Therefore, for reducing the electromagnetic noise, it is required to lower dV/dt or dI/dt during switching.
In a power semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as an “IGBT”), it is known that the relationship between saturation voltage and switching (turn-off) loss necessitates a trade-off. The saturation voltage to turn-off loss characteristics of necessitating a trade-off (hereinafter simply referred to as “trade-off characteristics”) become indices in evaluating a generated loss of a power semiconductor device.
Some effective measures for improving such trade-off characteristics have been proposed, such as increasing a carrier concentration near the surface of a power semiconductor device (for example, see JP-A-5-243561 (FIG. 101) and JP-A-2001-308327). In these techniques, a contact area of a semiconductor with an emitter electrode is decreased to increase a hole concentration in a base region, by which an IGBT with a lowered saturation voltage is realized. In the IGBT with such a structure, when the device is turned-on, carriers accumulate in a neighborhood of a region where the surface of the semiconductor is not in contact with the emitter electrode in a region interposed between trench structures.
Moreover, a semiconductor device with a structure in which a part of a gate insulator film is thickened is publicly known (for example, see Japanese Patent No. 3,325,424 or JP-A-2-102579). With such a structure, by thickening a portion of a gate insulator film contributing to gate-collector capacitance (hereinafter referred to as “GC capacitance”) more than the other portion, a portion contributing to gate-emitter capacitance (hereinafter referred to as “GE capacitance”), the GC capacitance can be made small. The GC capacitance and the GE capacitance make up gate capacitance.
Furthermore, in a lateral planer gate IGBT, there is publicly known one with a structure in which a P region is formed adjacent to a cathode side base zone so as to be separately positioned in an anode side n-base zone and the P region is connected to the cathode through a device having a non-linear current-voltage characteristic (for example, see JP-T-8-505008). According to this disclosure, such a structure is capable of enlarging a safe operating area (SOA) of the IGBT.
However, as disclosed in JP-A-5-243561 (FIG. 101) and JP-A-2001-308327, in the IGBT with the structure in which a carrier concentration near the surface is increased, gate capacitance near a region where carriers are accumulated when the IGBT is in conduction becomes GC capacitance. This results in an increase in the GC capacitance. Reduction in gate resistance for reducing a switching loss causes an increase in a rising speed of a gate voltage (charging speed of the GC capacitance) in an early stage of turning-on of the IGBT. This increases dI/dt of the IGBT and dV/dt of a diode in an opposing arm at turning-on of the IGBT. That is, there is a problem of increasing electromagnetic noise.
In addition, there is also a problem in that the small contact area of the semiconductor surface with the emitter electrode prevents carriers being swept out at turning-off of the IGBT to result in a large turn-off loss.
Furthermore, as is disclosed in Japanese Patent No. 3,325,424 or JP-A-2-102579, the thickening of a part of the gate oxide film causes problems of making the manufacturing method complicated and, in addition to this, of requiring a high processing accuracy.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.